1. Field of the Invention
The present invention relates to an information processing system provided with a self-diagnosing circuit, and more specifically to a self-diagnosing circuit for an information processing system controlled in accordance with microinstructions, which is particularly suitable for accurately evaluating AC performance of circuit blocks to be tested.
2. Description of the Prior Art
A self-test (i.e. self-diagnosis) technology has been developed to facilitate testing of circuit blocks (e.g. ROMs) formed in a large scale integrated circuit. In this self-test method, test data is self-generated and the test results are compressed for analysis (referred to as signature (test result) analysis). More specifically a test data generating circuit such as a linear feedback shift register (referred to as an LFSR) supplies test data in sequence to an objective circuit block to be tested in response to an external command, and then outputs the results from the circuit block which are then stored in a signature compressing circuit composed of an LFSR for signature compression. After a series of the above-mentioned operation has been executed, the compressed test results are compared with a previously prepared expected value for judging whether the circuit block is good or faulty.
FIG. 1 shows a CISC (Complex Instruction Set Computer) type microprocessor by way of an example to which the above-mentioned self-test can be applied. In this drawing, an objective circuit blocks 104 to be self-tested is shown, a signature compressing circuit 106 for storing the test results is also shown, and a test data generating circuit 105 is shown. All of these circuits are connected to an internal bus 101 in parallel. Further, a .mu.ROM 102 for storing a self-testing microprogram 102, a microinstruction register 130 for storing a microinstruction to be executed, and a microdecoder 103 for decoding a microinstruction stored in the microinstruction register 130 are all connected in series. Further, the decoded microinstructions are provided to the objective circuit blocks 104 and the signature compressing circuit 106.
In the microprocessor shown in FIG. 1, a plurality of circuit blocks 104 interconnected through the internal bus 101 are self-tested by the test data generating circuit 105 and the signature compressing circuit 106 also connected to the internal bus 101. The plural circuit blocks 104 are controlled by control signals obtained by decoding microinstructions stored at the self-testing microinstruction program storing area in the .mu.ROM 102 through the microinstruction decoder 103. Further, the test data generating circuit 105 and the signature compressing circuit 106 are also controlled by control signals obtained by similarly decoding microinstructions.
As described above, it is possible to systematically execute plural self-tests to a great number of circuit blocks, by controlling the structural elements required for self-test in accordance with microinstructions, in the same way as when the objective circuit blocks 104 to be tested are controlled, without increasing the number of structural elements required for testing.
In the microprocessor, however, since the microinstructions executed in the normal operation mode are not necessarily optimized as testing microinstructions in general, the number of steps of test microprograms prepared by use of the normal microinstructions is very large. To overcome this problem, there exists a self-test executable microprocessor configuration as shown in FIG. 2.
In the drawing, the multiplexers 110 and a counter 111 are supplied with the output signals from a self-test control circuit 112 and a self-test control information storing ROM 113. This controls these circuits in such a way that parts of microinstructions can be provided from the counter 111 and selected by the multiplexers 110, without generating other control signals by performing the microinstructions from a .mu.ROM 107 to a microinstruction decoder 109 via the microinstruction register 108. In the microprocessor shown in FIG. 2, since the number of microprogram words required for the testing can be decreased as compared with the number that would be required in the microprocessor shown in FIG. 1, it is possible to maximize the advantage of self-testing under the microinstruction control. In the microprocessor shown in FIG. 2, there is a problem in that the relative number of structural elements required to generate self-testing control signals increases.
Other problems involved in the prior art self-diagnosing circuits which are solved by the present invention will be explained in further detail below.
There exists recently a strong need for an evaluation mechanism which can effectively collect a great deal of evaluation data related to each circuit block arranged in an ultra-large scale integrated circuit. One of the most important evaluation data units is the AC operation performance or AC speed of the respective circuit blocks. Adequate evaluation and analysis related to the supply voltage, temperature, process parameter dependence, etc. play an important role in the effective improvement of production yield and effective development of more advanced microprocessors that have a higher performance ability.
When considering the general self-test from the standpoint of effective evaluation of AC performance, the microprocessor provided with self-test function is strictly restricted with respect to an increase in circuit forming area or space, because the test circuit itself must be formed on the same chip, so that the amount of test control information is inevitably restricted. Therefore, the test data to be supplied to the respective circuit blocks may not necessarily evaluate the full AC performance. In this self-test method, however, after a series of test data has been generated, since the test result obtained by applying the test data to each objective circuit block to be tested is evaluated by a single signature, it is possible to evaluate the basic AC performance of the respective circuit blocks in a very short time period, so that this self-test method can be effectively utilized for the above-mentioned object. The AC performance of the respective circuit blocks is normally measured in accordance with a Shmoo plot technique. The Shmoo plot technique will be explained in detail in the detailed description of the embodiments.
However, in a microinstruction controlled self-test for a 32-bit CISC-type high-performance microprocessor, there is a serious problem in that it is impossible to measure the AC performance of the objective circuit blocks to be tested at operation speeds beyond the AC performance of the self-test control block. In other words, there exists a severe limitation in the AC performance measurement of the above-mentioned high-speed microprocessor, differing from any usual self-test procedures. This problem, however, will not occur in the usual self-test procedure used by a relatively simple test control logic circuit, such as that for a memory unit.
In the case of microinstruction controlled self-testing, however, since the test microprograms descriptive of the execution control are usually stored in a part of a large-scale .mu.ROM, a problem arises in that the execution speed of the self-test is determined by the AC performance of the .mu.ROM, as indicated in FIG. 3. Namely, since the maximum operation frequency of the microinstruction controlled self-test cannot exceed the AC performance of the .mu.ROM, the true AC performance of each circuit block (represented by each bar graph) is only confirmed up to the extent represented by each of the hatched parts.
As a result, there exists a problem in that, although the true AC performance of the circuit blocks 1 and 4 which are lower in operation speed than the .mu.ROM can be measured, the AC performance of the other circuit blocks 2, 3, 5, 6 and 7 which are higher in operation speed than that of the .mu.ROM cannot be measured.
In a recent CISC type microprocessor, in particular, since the number of bits output and the number of words in a .mu.ROM tend to increase, it is rather difficult to provide an operation speed for the .mu.ROM that is sufficiently higher than that of all the objective circuit blocks to be self-tested. Therefore, there is a significant possibility of the existence of circuit blocks with a higher operational speed than the .mu.ROM (e.g. the circuit block 6 in FIG. 3). Therefore the test results for the circuit blocks with a higher speed than the .mu.ROM cannot be measured by the microinstruction controlled self-test executed via the .mu.ROM. This causes another problem in that other new circuit blocks are developed without refining or improving the already-developed circuit blocks to obtain the required higher performance. In addition, the above-mentioned problem also applies to circuit blocks which have an operation speed a little lower than the .mu.ROM but whose AC performance is strongly influenced by the process parameters.
To overcome these problems, it may be possible to successively evaluate AC performance by constructing scannable microinstruction registers, test data generating circuits, and signature compressing circuits by extending the BILBO (Built-in Logic Block Observer) technique. In this method, however, since the scanning design is based on serial data transfer, in the case of recent microprocessors provided with circuit blocks with multi-bit output connected to internal busses, it takes a large amount of time to effectively execute the failure diagnosis of these circuit blocks, so that the successive evaluation method is not suitable for the recently designed multi-bit microprocessors.
Conventionally, therefore, independent failure diagnosing circuits including AC performance evaluation are provided separately from the self-testing circuits for the circuit blocks to which the microinstruction controlled self-test is applied, where necessary at any cost. In addition, in this case, since it is impossible to adopt such a peculiar method whereby diagnostic microinstruction microprograms are stored in the .mu.ROM, there is another problem in that the amount of hardware for testing inevitably increases and therefore the overall system configuration becomes rather complicated.
Moreover, there is a serious problem in that it is difficult for a conventional LSI tester to test a circuit block which can operate at a high speed. A LSI tester which can operate at a frequency of 100 MHz is required to test one of the fastest circuit blocks at present which has an access time of approximately 10 nanoseconds.
However, an LSI tester is very expensive and its measuring accuracy is not necessarily adequate.